The present invention relates generally to computer systems. More particularly, the invention relates to a mechanism for synchronizing access to common resources.
An important requirement for a multiprocessor computer system is for multiple devices to be able to share a common resource. Typically, a synchronization mechanism is used to coordinate multiple accesses for the shared resource in order to ensure that one device obtains the shared resource at a given time.
An example of such a synchronization mechanism is an atomic instruction, such as a test-and-set instruction or a read-modify-write instruction. The atomic instruction operates on a lock variable or semaphore that represents the shared resource. Only one device is able to obtain access to the lock variable at a time thereby synchronizing access to the shared resource. Often, a device wants to write a value into the lock variable once it obtains access to it. The atomic instruction allows the device to both read the value of the lock variable and to write another value to the lock variable at the same time.
Atomic instructions are typically imp lemented using a bus lock mechanism or a cache coherency mechanism. In the bus lock mechanism, the bus is the only path to the memory location of the lock variable. A device obtains exclusive access to the bus thereby locking out all other devices to the memory location of the lock variable.
A cache coherency mechanism ensures that the contents of a particular memory location stored in any cache and in main memory remain coherent. In one such cache coherency mechanism, a protocol is used that updates the lock variable in one location in response to changes made to the lock variable in a second location. In another cache concurrency mechanism, another protocol is used that associates status tags with the lock variable that reflect the staleness of the lock variable when a copy of the lock variable is contained elsewhere. In this manner, a device is prevented from reading a copy of the lock variable that does not reflect its current value.
In some multiprocessor computer systems, a bus lock mechanism or a cache coherency mechanism may not be feasible. The shared resource and a device contending for the shared resource may not be connected by a common bus. In addition, the shared resource may not be cached thereby not subject to a cache coherency mechanism. For these types of computer systems, there is a need for a synchronization mechanism that can ensure atomic access to the shared resource.
In summary, the technology of the present invention pertains to a synchronization mechanism that controls multiple accesses to a shared resource. In an embodiment of the invention, a multiprocessor computer system embodying the synchronization mechanism has several processors coupled to a memory and I/O system that form a cell. The cells are coupled to each other through an interconnect such as a cross bar switch. The interconnect contains a number of shared resources, such as control and status registers, that can be accessed by any processor in order to initialize the routing information stored in the interconnect. These shared resources are non-cacheable by the processors.
In particular, when the computer system is powered on, any of the processors can initialize the routing information of the interconnect instead of relying on a dedicated processor to perform the task. In this manner, the interconnect will be initialized even in the event of a failure to any one of the processors. However, this benefit presents the problem of having multiple processors access the shared non-cacheable resource. Hence, the need for a synchronization mechanism to coordinate these accesses.
The interconnect includes a synchronization mechanism that utilizes a semaphore to control access to the shared resources. The synchronization mechanism includes a transaction control unit and a semaphore control unit. The transaction control unit serializes requests for access to the semaphore. The semaphore control unit initiates access to the semaphore. The semaphore is implemented by a pair of semaphore registers. A previous semaphore register is used to store the previous owner of the semaphore and a current semaphore register is used to either store the current owner of the semaphore or indicate that the semaphore is available.
A device, such as a processor, obtains access to a shared resource by making a request to write its unique identifier into the current semaphore register. When access is granted to the device, the device""s unique identifier is written into the current semaphore register. In order to determine if the device has obtained the shared resource, the device makes a subsequent request to read the contents of the current semaphore register . If the contents of the current semaphore register are the same as the device""s unique identifier then the device has successfully obtained access to the shared resource. Otherwise, the device has not yet received access to the shared resource and makes a subsequent request to obtain the semaphore.
To release access to a shared resource, the device having locked the semaphore writes a predefined unlock value into the current semaphore register. In the case where the device having locked the semaphore fails or is non-operational, an error handling mechanism can write the unlock value into the current semaphore register thereby unlocking the semaphore. When the semaphore is freed, the previous value of the semaphore is stored into the previous semaphore register.